查看“MYZR-SAMA5-CB200 硬件介绍”的源代码

= '''MY-SAMA5-CB200视图''' =
----
== '''正面视图''' ==
[[文件:MY-SAMA5-CB200_1.1.0.1.png|642px]]
== '''背面视图''' ==
[[文件:MY-SAMA5-CB200_1.2.0.1.png|642px]]
= '''SAMA5D3 MPU概览''' =
----
== '''SAMA5D3简介''' ==
　　Atmel | SMART SAMA5D3 MPU 能在低于 150mW 的功耗下提供高达 850DMIPS 的处理能力，是所有高性能、低功耗、成本敏感型工业应用的理想之选。其应用包括控制面板、智能电网设备和条形码扫描仪，即，需要高级别的连接性、增强的用户界面、稳定可靠的安全性或电池供电的任何设备。SAMA5D3 还是低功耗、小尺寸都至关重要的穿戴式计算应用和移动应用的理想之选。SAMA5D3 系列包括支持 -40/+105°C 温度范围以及 12x12mm BGA324 封装（间距为 0.5mm）的器件。<br>
　　Atmel | SMART™ SAMA5D3 系列以 536 Mhz 提供高达 850DMIPS 的处理能力，功耗水平市场领先（在工作模式下低于 150 mW；在低功耗模式下低于 0.5 mW）。通过支持高精度计算和快速数据处理的 FPU，以及 64 位内部总线架构和 32 位宽 DDR 控制器（能够以高达 166 MHz 的频率运行，提供高达 1328 MB/s 的带宽），实现了高性能。功能强大的外设包括多达三个的高速 USB 端口、千兆位和 10/100 以太网、双 CAN、TFT LCD 控制器、相机接口、三个 SDIO/SD/MMC、UART、SPI、TWI、软调制解调器、12 位 ADC、32 位定时器等。稳定可靠的安全性和防假冒由硬件加密引擎（如 AES/3DES、TRNG、SHA）和安全引导提供。这些器件随附免费 Atmel Linux® 分发包、Android 分发包、Qt SDK 以及一套完整的面向非操作系统用户的 C 示例。来自多个软件和硬件合作伙伴的 SOM（模块系统）、PMIC（电源管理IC）、内存和套件令本产品更加完整。<br>

== '''SAMA5D3优势''' ==
*ARM® Cortex®-A5 内核以 536MHz (850DMIPS) 运行。<br>
*用于高精度计算和快速数据处理的浮点运算单元 (FPU)。<br>
*市场领先的低功耗优势<br>
**在激活所有外设的情况下，以低于 150mW 的功耗（在工作模式下）提供高达 536MHz 的工作频率。<br>
**在具有 SRAM 和寄存器保留的情况下，低功耗模式下的功耗低于 0.5mW。<br>
**双 CAN 控制器。<br>
*支持 IEEE1588 的千兆位以太网 MAC 和 10/100 MAC。<br>
*三个 HS 高速 USB 端口（可配置为三个主机或两个主机和一个器件端口）。<br>
*CMOS 图像传感器接口。<br>
*图形 LCD 控制器，具有图像合成叠加<br>
*AES/3DES 硬件加密引擎和安全引导。<br>
*BGA324（15x15，间距为 0.8）封装，以及小封装选项 BGA（12x12mm，间距为 0.5）。<br>
*扩展的工业温度范围：-40°C 到 105°C。<br>

== '''SAMA5D3简图''' ==
[[文件:MY-SAMA5-CB200_2.3.0.1.png|642px]]
== '''SAMA5D3框图 ''' ==
[[文件:MY-SAMA5-CB200_2.4.0.1.png|642px]]
== '''SAMA5D3 MPU差异''' ==
[[文件:MY-SAMA5-CB200_2.5.0.1.png|642px]]
== '''SAMA5D36关键参数''' ==
{| class="wikitable"
|-
|Parameter	
|Value
|-
|Pin Count:	
|324
|-
|Max. Operating Freq. (MHz):	
|536 MHz
|-
|CPU:	
|Cortex-A5
|-
|Max I/O Pins:	
|160
|-
|Ext Interrupts:	
|160
|-
|USB Transceiver:	
|3
|-
|USB Speed:	
|Hi-Speed
|-
|USB Interface:	
|Host, Device
|-
|SPI:	
|6
|-
|TWI (I2C):	
|3
|-
|UART:	
|7
|-
|CAN:	
|2
|-
|LIN:	
|4
|-
|SSC:	
|2
|-
|Ethernet:	
|2
|-
|SD / eMMC:	
|3
|-
|Graphic LCD:	
|Yes
|-
|Camera Interface:	
|Yes
|-
|ADC Channels:	
|12
|-
|ADC Resolution (bits):	
|12
|-
|ADC Speed (ksps):	
|1000
|-
|Resistive Touch Screen:	
|Yes
|-
|Crypto Engine:	
|AES/DES/SHA/TRNG
|-
|SRAM (Kbytes):	
|128
|-
|External Bus Interface:	
|1
|-
|DRAM Memory:	
|DDR2/LPDDR/LPDDR2
|-
|NAND Interface:	
|Yes
|-
|Temp. Range (deg C):	
|－40 to 105
|-
|I/O Supply Class:	
|1.8/3.3
|-
|Operating Voltage (Vcc):	
|1.08 to 1.32
|-
|FPU:	
|Yes
|-
|Timers:	
|6
|-
|Output Compare Channels:	
|6
|-
|Input Capture Channels:	
|6
|-
|PWM Channels:	
|4
|-
|32kHz RTC:	
|Yes
|-
|MPU / MMU:	
|No / Yes
|-
|Quadrature Decoder Channels:	
|0
|-
|Video Decoder:	
|No
|}

= '''MY-IMX6-CB200配置''' =
== '''硬件配置''' ==
----
{| class="wikitable"
|-
|CPU	
|SAMA5D3x	
|工业级/扩展工业级
|-
|内存	
|256MB	
|可扩展到512MB
|-
|存储	
|256MB	
|最大可支持到2GB
|-
|SPI Flash	
|2M	
|支持烧录
|-
|启动模式	
|SPI启动	
|确保产品的稳定可靠
|}

== '''工作温度范围''' ==
*工业级<br>
		　　　 -40°C ~ 85°C<br>
*扩展工业级<br>
		　　　 -40°C ~ 105°C<br>

== '''操作系统支持''' ==
*内核：Linux-3.18<br>
*界面：命令行，QT5<br>
== '''型号命令''' ==
=== 型号名称组成 ===
MY-SAMA5-CB200-MPU规格-内存容量-存储容量<br>
=== MPU规格 ===
D36ACN, D36ACNR: 工业扩展级<br>
D36ACU, D36ACUR: 工业级<br>
=== 内存容量 ===
256MB: 256兆内存<br>
=== 存储容量 ===
256MB: 256兆存储<br>
=== 型号举例 ===
MY-SAMA5-CB200-D36ACN-256M-256M <br>

= '''MY-SAMA5-CB200定义''' =
{| class="wikitable" 
|-
!序号<br>Num
!引脚<br>Pin	
!默认信号<br>Default signal
!默认接口<br>Default Interface
!可复用的信号<br>Multiplex||　
!可复用的信号<br>Multiplex
!默认接口<br>Default Interface
!默认信号<br>Default signal
!引脚<br>Pin
!序号<br>Num.
|-
|1	||GND_POWER	||　	||　	||　	||　	||　	||　	||　	||GND_POWER	||2
|-
|3	||PC1	||ETX1	||rowspan=10|EMAC	||TIOB3	||　	||LCDDAT19	
|rowspan=6|MCI2	
|MCI2_DA0	
|PC11	
|4
|-
|5	||PC8	||EMDC	
	
|TCLK5	
|　	
|LCDDAT18｜TIOA1	
	
|MCI2_DA1	
|PC12	
|6
|-
|7	
|PC3	
|ERX1	
	
|TIOA4	
|　	
|LCDDAT21｜PCK2	
	
|MCI2_CK	
|PC15	
|8
|-
|9	
|PC6	
|ERXER	
	
|TIOA5	
|　	
|LCDDAT17｜TIOB1	
	
|MCI2_DA2	
|PC13	
|10
|-
|11	
|PC4	
|ETXEN	
	
|TIOB4	
|　	
|LCDDAT20	
	
|MCI2_CDA	
|PC10	
|12
|-
|13	
|PC7	
|EREFCK	
	
|TIOB5	
|　	
|LCDDAT16｜TCLK1	
	
|MCI2_DA3	
|PC14	
|14
|-
|15	
|PC0	
|ETX0	
	
|TIOA3	
|　	
|　	
|rowspan=6|SSC0	
|RK0	
|PC19	
|16
|-
|17	||PC2	||ERX0		||TCLK3	||　	||	||TF0	||PC17	||18
|-
|19	
|PC5	
|ECRSDV	
	
|TCLK4	
|　	　	
|	
|RF0	
|PC20	
|20
|-
|21	
|PC9	
|EMDIO	
	
|　	
|　	
|　	
	
|RD0	
|PC21	
|22
|-
|23	
|PC30	
|UTXD0	
|rowspan=2|UART0	
|ISI_PCK	
|　	
|　	
	
|TK0	
|PC16	
|24
|-
|25	
|PC29	
|URXD0	
	
|ISI_D8｜PWMFI2	
|　	
|　	
	
|TD0	
|PC18	
|26
|-
|27	
|GND_POWER	
|　	
|　	
|　	
|　	
|　	
|　	
|　	
|GND_POWER	
|28
|-
|29	
|PC31	
|　	
|　	
|PWMFI1｜FIQ	
|　	
|　	
|rowspan=2|LCDC	
|LCDVSYNC	
|PA26	
|30
|-
|31 ||PC23 ||SPI1_MOSI ||rowspan=5|SPI1 ||　 　 ||　 || ||LCDDISP ||PA25 ||32
|-
|33 ||PC25 ||SPI1_NPCS0  ||　 ||　 ||　 ||　 ||　 ||GND_POWER ||34
|-
|35 ||PC22 ||SPI1_MISO  ||　 ||　 ||　 ||LCDC ||LCDHSYNC ||PA27 ||36
|-
|37 ||PC24 ||SPI1_SPCK  ||　 ||　 ||　 ||　 ||　 ||GND_POWER ||38
|-
|39 ||PC28 ||SPI1_NPCS3  ||ISI_D9｜PWMFI0 ||　 ||　 ||rowspan=15|LCDC ||LCDDEN ||PA29 ||40
|-
|41 ||PA4 ||LCDDAT4 ||rowspan=12|LCDC ||　 ||　 ||　  ||LCDDAT2 ||PA2 ||42
|-
|43 ||PA10 ||LCDDAT10  ||　 ||　 ||　  ||LCDDAT15 ||PA15 ||44
|-
|45 ||PA14 ||LCDDAT14  ||　 ||　 ||ISI_D1  ||LCDDAT17 ||PA17 ||46
|-
|47 ||PA12 ||LCDDAT12  ||　 ||　 ||　  ||LCDDAT1 ||PA1 ||48
|-
|49 ||PA24 ||LCDPWM  ||　 ||　 ||　  ||LCDDAT0 ||PA0 ||50
|-
|51 ||PA22 ||LCDDAT22  ||ISI_D6｜PWMH1 ||　 ||　  ||LCDDAT3 ||PA3 ||52
|-
|53 ||PA28 ||LCDPCK  ||　 ||　 ||　  ||LCDDAT8 ||PA8 ||54
|-
|55 ||PA20 ||LCDDAT20  ||ISI_D4｜PWMH0 ||　 ||　  ||LCDDAT6 ||PA6 ||56
|-
|57 ||PA21 ||LCDDAT21  ||ISI_D5｜PWML0 ||　 ||ISI_D2｜TWD2  ||LCDDAT18 ||PA18 ||58
|-
|59 ||PA23 ||LCDDAT23  ||ISI_D7｜PWML1 ||　 ||ISI_D0  ||LCDDAT16 ||PA16 ||60
|-
|61 ||PA5 ||LCDDAT5  ||　 ||　 ||ISI_D3｜TWCK2  ||LCDDAT19 ||PA19 ||62
|-
|63 ||PA7 ||LCDDAT7  ||　 ||　 ||　  ||LCDDAT11 ||PA11 ||64
|-
|65 ||PA30 ||TWD0 ||rowspan=2|TWI0 ||URXD1｜ISI_VSYNC ||　 ||　  ||LCDDAT9 ||PA9 ||66
|-
|67 ||PA31 ||TWCK0  ||UTXD1｜ISI_HSYNC ||　 ||　  ||LCDDAT13 ||PA13 ||68
|-
|69 ||PD31 ||　 ||　 ||PCK1｜AD11 ||　 ||ISI_D10｜SPI1_NPCS2 ||rowspan=2|TWI1 ||TWCK1 ||PC27 ||70
|-
|71 ||PD30 ||PCK0 ||SSC0:CLK ||AD10 ||　 ||ISI_D11｜SPI1_NPCS1  ||TWD1 ||PC26 ||72
|-
|73 ||PD29 ||AD9 ||rowspan=10|AD ||　 ||　 ||　 ||rowspan=8|MCI0 ||MCI0_DA3 ||PD4 ||74
|-
|75 ||PD28 ||AD8 || 　 ||　 ||　  ||MCI0_DA1 ||PD2 ||76
|-
|77 ||PD27 ||AD7 || 　 ||　 ||　  ||MCI0_CDA ||PD0 ||78
|-
|79 ||PD26 ||AD6 || 　 ||　 ||　  ||MCI0_CK ||PD9 ||80
|-
|81 ||PD23 ||AD3 || 　 ||　 ||　  ||MCI0_DA2 ||PD3 ||82
|-
|83 ||PD22 ||AD2 || 　 ||　 ||　  ||MCI0_DA0 ||PD1 ||84
|-
|85 ||PD24 ||AD4 || 　 ||　 ||PWML2｜TIOB0  ||MCI0_DA5 ||PD6 ||86
|-
|87 ||PD21 ||AD1 || 　 ||　 ||PWML3  ||MCI0_DA7 ||PD8 ||88
|-
|89 ||PD25 ||AD5 || 　 ||　 ||SPI0_NPCS2｜CTS0 ||rowspan=2|CAN0 ||CANTX0 ||PD15 ||90
|-
|91 ||PD20 ||AD0 || 　 ||　 ||SPI0_NPCS1｜SCK0  ||CANRX0 ||PD14 ||92
|-
|93 ||PD5 ||PWMH2 ||rowspan=2|PWM ||MCI0_DA4｜TIOA0 ||　 ||　 ||UART0 ||TXD0 ||PD18 ||94
|-
|95 ||PD7 ||PWMH3  ||MCI0_DA6｜TCLK0 ||　 ||　 || ||RXD0 ||PD17 ||96
|-
|97 ||PD19 ||　 ||GPIO ||ADTRG ||　 ||　 ||rowspan=3|SPI0 ||SPI0_MISO ||PD10 ||98
|-
|99 ||PB0 ||GTX0 ||rowspan=15|GMAC ||PWMH0 ||　 　 || ||SPI0_SPCK ||PD12 ||100
|-
|101 ||PB7 ||GRX3  ||RK1 ||　 ||　  ||SPI0_MOSI ||PD11 ||102
|-
|103 ||PB13 ||GRXER  ||PWML3 ||　 ||PWMH3｜GRXDV ||GMAC:INTRP ||　 ||PB12 ||104
|-
|105 ||PB17 ||GMDIO  ||　 ||　 ||GCOL ||rowspan=2|CAN0 ||CANTX1 ||PB15 ||106
|-
|107 ||PB11 ||GRXCK  ||RD1 ||　 ||GCRS  ||CANRX1 ||PB14 ||108
|-
|109 ||PB18 ||G125CK  ||　 ||　 ||GTX7 ||rowspan=6|MCI1 ||MCI1_DA2 ||PB22 ||110
|-
|111 ||PB1 ||GTX1  ||PWML0 ||　 ||GRX5   ||MCI1_CK ||PB24 ||112
|-
|113 ||PB4 ||GRX0  ||PWMH1 ||　 ||GTX5   ||MCI1_DA0 ||PB20 ||114
|-
|115 ||PB3 ||GTX3  ||TF1 ||　 ||GTX6   ||MCI1_DA1 ||PB21 ||116
|-
|117 ||PB8 ||GTXCK  ||PWMH2 ||　 ||GTX4   ||MCI1_CDA ||PB19 ||118
|-
|119 ||PB9 ||GTXEN  ||PWML2 ||　 ||GRX4   ||MCI1_DA3 ||PB23 ||120
|-
|121 ||PB2 ||GTX2  ||TK1 ||　 ||G125CKO ||rowspan=4|USART1 ||RTS1 ||PB27 ||122
|-
|123 ||PB6 ||GRX2  ||TD1 ||　 ||　  ||RXD1 ||PB28 ||124
|-
|125 ||PB5 ||GRX1  ||PWML1 ||　 ||　  ||TXD1 ||PB29 ||126
|-
|127 ||PB16 ||GMDC  ||　 ||　 ||GRX7 ||CTS1 ||PB26 ||128
|-
|129 ||PB25 ||　 ||　 ||SCK1｜GRX6 ||　 ||RF1｜GTXER ||EMAC:INT_N ||　 ||PB10 ||130
|-
|131 ||BMS ||　 ||　 ||　 ||　 ||　 ||　 ||　 ||DIBN ||132
|-
|133 ||NRST ||　 ||　 ||　 ||　 ||　 ||　 ||　 ||DIBP ||134
|-
|135 ||TDI ||　 ||　 ||　 ||　 ||　 ||rowspan=2|DEBUG ||DTXD ||PB31 ||136
|-
|137 ||JTAGSEL ||　 ||　 ||　 ||　 ||　  ||DRXD ||PB30 ||138
|-
|139 ||TCK ||SWCLK ||　 ||　 ||　 ||PWMFI3|SPI0_NPCS3｜RTS0 ||SSC0:IRQ ||　 ||PD16 ||140
|-
|141 ||TMS ||SWDIO ||　 ||　 ||　 ||　 ||　 ||　 ||GND_POWER ||142
|-
|143 ||TDO ||　 ||　 ||　 ||　 ||　 ||USBA ||DHSDP ||HHSDPA ||144
|-
|145 ||NTRST ||　 ||　 ||　 ||　 ||　 || ||DHSDM ||HHSDMA ||146
|-
|147 ||WKUP ||　 ||　 ||　 ||　 ||　 ||USBB ||　 ||HHSDPB ||148
|-
|149 ||SHDN ||　 ||　 ||　 ||　 ||　 || ||　 ||HHSDMB ||150
|-
|151 ||D7 ||　 ||rowspan=8|EBI:Dx ||　 ||　 ||　 ||USBC ||　 ||HHSDMC ||152
|-
|153 ||D6 ||　  ||　 ||　 ||　 || ||　 ||HHSDPC ||154
|-
|155 ||D5 ||　  ||　 ||　 ||LCDDAT23｜TIOB2 ||rowspan=10|EBI ||NCS2 ||PE28 ||156
|-
|157 ||D4 ||　  ||　 ||　 ||LCDDAT22｜TIOA2  ||NCS1 ||PE27 ||158
|-
|159 ||D3 ||　  ||　 ||　 ||USART2:CTS2  ||A23 ||PE23 ||160
|-
|161 ||D2 ||　  ||　 ||　 ||USART2:RXD2  ||A25 ||PE25 ||162
|-
|163 ||D1 ||　  ||　 ||　 ||USART2:TXD2  ||NCS0 ||PE26 ||164
|-
|165 ||D0 ||　  ||　 ||　 ||　  ||A20 ||PE20 ||166
|-
|167 ||PE3 ||A3 ||rowspan=11|EBI:Ax ||GPIO:LED ||　 ||USART2:RTS2  ||A24 ||PE24 ||168
|-
|169 ||PE5 ||A5 || 　 ||　 ||TCLK2  ||NWR1/NBS1 ||PE29 ||170
|-
|171 ||PE6 ||A6 || 　 ||　 ||USART3:RXD3  ||A18 ||PE18 ||172
|-
|173 ||PE13 ||A13 || 　 ||　 ||USART3:TXD3  ||A19 ||PE19 ||174
|-
|175 ||PE15 ||A15  ||SCK3 ||　 ||PWML1｜IRQ ||MMC1:VDD_EN ||　 ||PE31 ||176
|-
|177 ||PE8 ||A8  ||　 ||　 ||NWAIT ||MMC1:CD ||　 ||PE30 ||178
|-
|179 ||PE10 ||A10  ||　 ||　 ||GPIO:LED ||rowspan=7|EBI:Ax ||A4 ||PE4 ||180
|-
|181 ||PE14 ||A14  ||　 ||　 ||GPIO:LED  ||A2 ||PE2 ||182
|-
|183 ||PE16 ||A16  ||CTS3 ||　 ||GPIO:LED  ||A1 ||PE1 ||184
|-
|185 ||PE0 ||A0/NBS0  ||　 ||　 ||　  ||A7 ||PE7 ||186
|-
|187 ||PE11 ||A11  ||　 ||　 ||RTS3  ||A17 ||PE17 ||188
|-
|189 ||GND_POWER ||　 ||　 ||　 ||　 ||　  ||A9 ||PE9 ||190
|-
|191 ||GND_POWER ||　 ||　 ||　 ||　 ||　  ||A12 ||PE12 ||192
|-
|193 ||GND_POWER ||　 ||　 ||　 ||　 ||　 ||　 ||　 ||VCC_3V3 ||194
|-
|195 ||GND_POWER ||　 ||　 ||　 ||　 ||　 ||　 ||　 ||VCC_3V3 ||196
|-
|197 ||GND_POWER ||　 ||　 ||　 ||　 ||　 ||　 ||　 ||VCC_3V3 ||198
|-
|199 ||GND_POWER ||　 ||　 ||　 ||　 ||　 ||　 ||　 ||VCC_3V3 ||200
|-
|colspan=11|说明1：“可复用的信号”栏中黄色背景表示在MY-SAMA5-EK200上实现的信号。
|-
|colspan=11|说明2：MY-SAMA5-CB200-D36引出的管脚主要有PA0~PA31、PB0~PB31、PC0~PC31、PD0~PD12、PD14~PD31、PE0~PE20、PE23~PE31。
|}

= '''SAMA5D3 MPU介绍''' =
----
== '''SAMA5关键亮点''' ==
=== 高性能 ===
　　SAMA5 系列是专为弥补 ARM Cortex-A5 内核在功率方面的不足而设计，包括的器件能以低至 150 mW 的功耗提供高达 945DMIPS 的处理能力。<br>
:*1.58 DMIPS/MHz ARM Cortex-A5 内核<br>
:*高达 600 MHz 的最大工作频率 (945DMIPS)<br>
:*64 位内部总线架构、可提供高达 1600 MB/s 带宽的 32 位宽 DDR 控制器<br>
:*用于高精度计算和快速数据处理的 Neon 和浮点运算单元 (FPU)<br>
:*ARM Cortex-A5 FPU 的性能是 ARM Cortex-A8 FPU 的三倍<br>
:*L2 缓存，用于提高整体系统性能<br>

=== 低功耗 ===
　　SAMA5 器件采用创新技术以降低所有模式下的功耗，并且可实现：<br>
:*在激活所有外设的情况下，以低于 150mW 的功耗（在工作模式下）提供高达 536MHz 的工作频率<br>
:*在运行 SRAM 和 寄存器保留的低功耗模式下，功耗低于 0.5mW 且唤醒时间短于 0.5ms。在运行 RTC（实时时钟）的备份模式下功耗约为 1.2µA<br>
:*电池供电系统的理想之选<br>

=== 连接性 ===
　　SAMA5 器件嵌入了各种高级通信外设，因此是网桥和网关的理想之选。<br>
:*支持 IEEE1588 的以太网 MAC 和千兆位以太网 MAC、双 CAN 端口<br>
:*可配置为三个主机或两个主机及一个器件端口的三个高速 USB 端口<br>
:*多个 SDIO/SD/MMC 端口、UART、SPI、TWI、软调制解调器、CMOS 图像传感器接口、ADC、32 位定时器等。有关更多详细信息，请参阅“器件概述”选项卡<br>

=== 增强的用户界面 ===
　　使用 SAMA5 MPU，可以创建当今应用所需的时尚、平稳的用户界面。<br>
:*图形 LCD 控制器具有图像合成叠加和集成功能（如 α 混合、缩放、颜色转换和旋转）<br>
:*720p 硬件视频解码器，用于加快支持当今主流视频标准的视频回放<br>
:*电阻式触摸屏界面<br>
:*CMOS 图像传感器接口<br>

=== 安全 ===
　　SAMA5 系列包括防止克隆、确保真实性以及保护应用的通信和数据存储安全的功能。<br>
:*安全引导<br>
:*硬件加密引擎，如高级加密标准 (AES)/三重数据加密标准 (DES)、RSA (Rivest-Shamir-Adleman) 和 ECC（椭圆曲线加密）以及安全哈希算法 (SHA) 和真正的随机号码生成器 (TRNG)<br>
:*通过外部 DDR 内存即时加密/解密代码<br>
:*管脚篡改检测，以保护系统免受物理入侵<br>
:*密钥和数据的安全存储<br>
:*ARM 信任区域，用于对系统、外设和内存资源进行分区，以将安全关键型软件与开放环境操作系统隔离<br>

=== 安全性 ===
　　SAMA5 系列具有的功能可轻松简便地实施如 IEC61508 等安全标准。<br>
:*主晶体振荡器时钟具有故障检测器<br>
:*上电复位<br>
:*独立的看门狗定时器<br>
:*寄存器写保护<br>
:*内存管理单元 (MMU) 允许在内存内设置区域保护<br>
:*基于 SHA 的 ICM（完整性检查监控器），用于验证内存内容的完整性<br>
:*Arm 信任区域<br>

=== 低系统成本 ===
　　SAMA5 凭借高度的系统集成，在实现最大灵活性的同时还减少了对其他昂贵组件的需求。<br>
:*0.8mm 球间距封装简化了 PCB 设计并降低了成本<br>
:*最低功耗方案，需要芯片离散的电源或低成本 PMIC<br>
:*三个高速 USB 端口节省了外部集线器的成本<br>
:*DDR（双数据速率）内存线路上的阻抗控件节省了外部电阻器<br>
:*嵌入式 RTC 节省了外部组件<br>
:*集成的软调制解调器解决方案节省了外部调制解调器设备的成本<br>

== '''SAMA5D3 Features''' ==
=== Core ===
:*ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set<br>
:**CPU Frequency up to 536 MHz <br>
:*32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)<br>
:*Fully Integrated MMU and Floating Point Unit (VFPv4)<br>

=== Memories ===
:*One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on 8-bit <br>
:*NAND Flash, SDCard, eMMC, serial DataFlash®, selectable Order <br>
:*One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed<br>
:*High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 with datapath scrambling<br>
:*Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC)<br>
=== System running up to 166 MHz  ===
:*Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock<br>
:*Boot Mode Select Option, Remap Command<br>
:*Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator<br>
:*Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator<br>
:*One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimize d for USB High Speed<br>
:*39 DMA Channels including two 8-channel 64-bit Central DMA Controllers<br>
:*64-bit Advanced Interrupt Controller<br>
:*Three Programmable External Clock Signals<br>
:*Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer<br>
=== Low Power Management ===
:*Shut Down Controller <br>
:*Battery Backup Registers<br>
:*Clock Generator and Power Management Controller<br>
:*Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities<br>
=== Peripherals ===
:*LCD TFT Controller with Overlay, Alpha-blending,Rotation, Scaling and Color Space Conversion<br>
:*ITU-R BT. 601/656 Image Sensor Interface<br>
:*Three HS/FS/LS USB Ports with On-Chip Transceivers<br>
:**One Device Controller <br>
:**One Host Controller with Integrated Root Hub (3 Downstream Ports)<br>
:*One 10/100/1000 Mbps Gigabit Ethernet MAC Controller (GMAC) with IEEE1588 support<br>
:*One 10/100 Mbps Ethernet MAC Controller (EMAC)<br>
:*Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B<br>
:*Softmodem Interface<br>
:*Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)<br>
:*Two Master/Slave Serial Peripheral Interfaces<br>
:*Two Synchronous Serial Controllers<br>
:*Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS<br>
:*Four USARTs, two UARTs, one DBGU <br>
:*Two Three-channel 32-bit Timer/Counters<br>
:*One 4-channel 16-bit PWM Controller<br>
:*One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function<br>

=== Safety ===
:*Power-on Reset Cells<br>
:*Independent Watchdog<br>
:*Main Crystal Clock Failure Detection<br>
:*Write Protection Registers<br>
:*SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA 256, SHA384, SHA512)<br>
:*Memory Management Unit<br>
=== Security ===
:*TRNG: True Random Number Generator <br>
:*Encryption Engine<br>
:**AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications <br>
:**TDES: Two-key or Three-key Algorithms, Co mpliant with FIPS PUB 46-3 Specifications<br>
:*Atmel® Secure Boot Solution<br>

=== I/O ===
:*Five 32-bit Parallel Input/Output Controllers<br>
:*160 I/Os<br>
:*Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input<br>
:*Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering<br>
:*Slew Rate Control on High Speed I/Os<br>
:*Impedance Control on DDR I/Os<br>
=== Package ===
:*324-ball LFBGA, 15 x 15 x 1.4 mm, pitch 0.8 mm<br>
:*324-ball TFBGA, 12 x 12 x 1.2 mm, pitch 0.5 mm<br>

== '''SAMA5D3 Embedded Characteristics''' ==

=== WDT ===
:*12-bit key-protected programmable counter<br>
:*Watchdog Clock is independent from Processor Clock<br>
:*Provides reset or interrupt signals to the system<br>
:*Counter may be stopped while the processor is in debug state or in idle mode<br>
=== RTC ===
:*Ultra Low Power Consumption<br>
:*Full Asynchronous Design<br>
:*Gregorian Calendar up to 2099 <br>
:*Programmable Periodic Interrupt<br>
:*Safety/security features:<br>
:**Valid Time and Date Programmation Check<br>

=== PIO ===
:*Up to 32 Programmable I/O Lines<br>
:*Fully Programmable through Set/Clear Registers <br>
:*Multiplexing of Four Peripheral Functions per I/O Line<br>
:*For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)<br>
:**Input Change Interrupt <br>
:**Programmable Glitch Filter<br>
:**Programmable Debouncing Filter<br>
:**Multi-drive Option Enables Driving in Open Drain<br>
:**Programmable Pull-Up on Each I/O Line<br>
:**Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time<br>
:**Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-Level<br>
:**Lock of the Configuration by the Connected Peripheral<br>
:*Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write<br>
:*Register Write Protection<br>
:*Programmable Schmitt Trigger Inputs<br>
:*Programmable I/O Drive<br>

=== LCDC ===
:*Dual AHB Master Interface <br>
:*Supports Single Scan Active TFT Display<br>
:*Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit<br>
:*Asynchronous Output Mode Supported (at synthesis time)<br>
:*1, 2, 4, 8 bits per pixel (palletized)<br>
:*12, 16, 18, 19, 24, 25 and 32 bits per pixel (non palletized)<br>
:*Supports One Base Layer (background)<br>
:*Supports Two Overlay Layer Windows<br>
:*Supports One High End Overlay (HEO) Window<br>
:*Supports One Hardware Cursor, Fixed or Free Size<br>
:*Hardware Cursor Fixed Size on the following patterns: 32x32, 64x64 and 128x128<br>
:*Little Endian Memory Organization<br>
:*Programmable Timing Engine, with Integer Clock Divider<br>
:*Programmable Polarity for Data, Line Synchro and Frame Synchro.<br>
:*Display Size up to 2048x2048, or up to 720p in video format<br>
:*Color Lookup Table with up to 256 entries and Predefined 8-bit Alpha<br>
:*Programmable Negative and Positive Row Striding for all Layers<br>
:*Programmable Negative and Positive Pixel Striding for all Overlay1, Overlay2 and HEO layers<br>
:*High End Overlay supports 4:2:0 Planar Mode and Semiplanar Mode<br>
:*High End Overlay supports 4:2:2 Planar Mode, Semiplanar Mode and Packed<br>
:*High End Overlay includes Chroma Upsampling Unit<br>
:*Horizontal and Vertical Rescaling unit with Edge Interpolation and Independent Non Integer Ratio<br>
:*Hidden Layer Removal supported.<br>
:*Integrates Fully Programmable Color Space Conversion<br>
:*Overlay1, Overlay2 and High End Overlay Integrate Rotation Engine: 90, 180, 270<br>
:*Blender Function Supports Arbitrary 8-bit Alpha Value and Chroma Keying<br>
:*DMA User interface uses Linked List Structure and Add-to-queue Structure<br>
=== ISI ===
:*ITU-R BT. 601/656 8-bit Mode External Interface Support<br>
:*Supports up to 12-bit Grayscale CMOS Sensors<br>
:*Support for ITU-R BT.656-4 SAV and EAV Synchronization<br>
:*Vertical and Horizontal Resolutions up to 2048*2048<br>
:*Preview Path<br>
:**Up to 2048*2048 in Grayscale Mode<br>
:**Up to 640*480 in RGB Mode<br>
:*32 Bytes FIFO on Codec Path<br>
:*32 Bytes FIFO on Preview Path<br>
:*Support for Packed Data Formatting for YCbCr 4:2:2 Formats<br>
:*Preview Scaler to Generate Smaller Size image<br>
:*Programmable Frame Capture Rate<br>
:*VGA, QVGA, CIF, QCIF Formats Supported for LCD Preview<br>
:*Custom Formats with Horizontal and Vertical Preview Size as Multiples of 16 Also Supported for LCD Preview<br>

=== UDPHS ===
:*1 Device High Speed<br>
:*1 UTMI transceiver shared between Host and Device<br>
:*USB v2.0 High Speed Compliant, 480 Mbit/s<br>
:*16 Endpoints up to 1024 bytes<br>
:*Embedded Dual-port RAM for Endpoints<br>
:*Suspend/Resume Logic (Command of UTMI)<br>
:*Up to Three Memory Banks for Endpoints (Not for Control Endpoint)<br>
:*8 KBytes of DPRAM<br>
=== UHPHS ===
:*Compliant with Enhanced HCI Rev 1.0 Specification<br>
:**Compliant with USB V2.0 High-speed <br>
:**Supports High-speed 480 Mbps<br>
:*Compliant with OpenHCI Rev 1.0 Specification<br>
:**Compliant with USB V2.0 Full-speed and Low-speed Specification<br>
:**Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices<br>
:*Root Hub Integrated with 3 Downstream USB HS Ports <br>
:*Embedded USB Transceivers<br>
:*Supports Power Management<br>
:*Hosts (A and B) High Speed (EHCI), Port A shared with UDPHS<br>

=== GMAC ===
:*Compatible with IEEE Standard 802.3<br>
:*10, 100 and 1000 Mbps operation<br>
:*Full and half duplex operation at all supported speeds of operation<br>
:*Statistics Counter Registers for RMON/MIB<br>
:*MII/GMII/RGMII interface to the physical layer<br>
:*Integrated physical coding<br>
:*Direct memory access (DMA) interface to external memory<br>
:*Programmable burst length and endianism for DMA<br>
:*Interrupt generation to signal receive and transmit completion, or errors<br>
:*Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames<br>
:*Frame extension and frame bursting at 1000 Mbps in half duplex mode<br>
:*Automatic discard of frames received with errors<br>
:*Receive and transmit IP, TCP and UDP checksum offload. Both IPv4 and IPv6 packet types supported<br>
:*Address checking logic for four specific 48-bit addresses, four type IDs, promiscuous mode, hash matching of <br>
:*unicast and multicast destination addresses and Wake-on-LAN<br>
:*Management Data Input/Output (MDIO) interface for physical layer management<br>
:*Support for jumbo frames up to 10240 bytes<br>
:*Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause <br>
:*frames<br>
:*Half duplex flow control by forcing collisions on incoming frames<br>
:*Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames<br>
:*Support for 802.1Qbb priority-based flow control<br>
:*Programmable Inter Packet Gap (IPG) Stretch <br>
:*Recognition of IEEE 1588 PTP frames<br>
:*IEEE 1588 time stamp unit (TSU)<br>
:*Support for 802.1AS timing and synchronization<br>
=== EMAC ===
:*Supports RMII Interface to the physical layer<br>
:*Compatible with IEEE Standard 802.3<br>
:*10 and 100 Mbit/s Operation<br>
:*Full-duplex and Half-duplex Operation<br>
:*Statistics Counter Registers<br>
:*Interrupt Generation to Signal Receive and Transmit Completion<br>
:*DMA Master on Receive and Transmit Channels<br>
:*Transmit and Receive FIFOs<br>
:*Automatic Pad and CRC Generation on Transmitted Frames<br>
:*Automatic Discard of Frames Received with Errors<br>
:*Address Checking Logic Supports Up to Four Specific 48-bit Addresses<br>
:*Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory<br>
:*Hash Matching of Unicast and Multicast Destination Addresses<br>
:*Physical Layer Management through MDIO Interface<br>
:*Half-duplex Flow Control by Forcing Collisions on Incoming Frames<br>
:*Full-duplex Flow Control with Recognition of Incoming Pause Frames <br>
:*Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames<br>
:*Multiple Buffers per Receive and Transmit Frame<br>
:*Wake-on-LAN Support<br>
:*Jumbo Frames Up to 10240 bytes Supported<br>
=== HSMCI === 
:*Compatible with MultiMedia Card Specification Version 4.3<br>
:*Compatible with SD Memory Card Specification Version 2.0<br>
:*Compatible with SDIO Specification Version 2.0<br>
:*Compatible with CE-ATA Specification 1.1<br>
:*Cards Clock Rate Up to Master Clock Divided by 2<br>
:*Boot Operation Mode Support<br>
:*High Speed Mode Support<br>
:*Embedded Power Management to Slow Down Clock Rate When Not Used<br>
:*Supports 1 Multiplexed Slot(s)<br>
:**Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card<br>
:*Support for Stream, Block and Multi-block Data Read and Write<br>
:*Supports Connection to DMA Controller (DMAC)<br>
:**Minimizes Processor Intervention for Large Buffer Transfers<br>
:*Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access<br>
:*Support for CE-ATA Completion Signal Disable Command<br>
:*Protection Against Unexpected Modification On -the-Fly of the Configuration Registers<br>
=== SPI === 
:*Supports Communication with Serial External Devices<br>
:**Master Mode can drive SPCK up to peripheral clock (bounded by maximum bus clock divided by 2)<br>
:**Slave Mode operates on SPCK, asynchronously to Core and Bus Clock<br>
:**Four Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals<br>
:**Serial Memories, such as DataFlash and 3-wire EEPROMs<br>
:**Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors<br>
:**External Coprocessors<br>
:*Master or Slave Serial Peripheral Bus Interface<br>
:**8-bit to 16-bit Programmable Data Length Per Chip Select<br>
:**Programmable Phase and Polarity Per Chip Select<br>
:**Programmable Transfer Delay Between Consecutive Transfers and Delay before SPI Clock per Chip Select<br>
:**Programmable Delay Between Chip Selects<br>
:**Selectable Mode Fault Detection<br>
:*Connection to DMA Channel Capabilities Optimizes Data Transfers<br>
:**One channel for the Receiver, One Channel for the Transmitter<br>
=== TWI === 
:*3 TWIs <br>
:*Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices<br>
:*One, Two or Three Bytes for Slave Address<br>
:*Sequential Read-write Operations<br>
:*Master, Multi-master and Slave Mode Operation<br>
:*Bit Rate: Up to 400 Kbit/s<br>
:*General Call Supported in Slave mode<br>
:*SMBUS Quick Command Supported in Master Mode<br>
:*Connection to DMA Controller (DMA) Channel Capabilities Optimizes Data Transfers<br>
=== SSC === 
:*Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications <br>
:*Contains an Independent Receiver and Transmitter and a Common Clock Divider<br>
:*Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead<br>
:*Offers a Configurable Frame Sync and Data Length<br>
:*Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different Events on the <br>
:*Frame Sync Signal<br>
:*Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal<br>
=== DBGU === 
:*System Peripheral to Facilitate Debug of Atmel® ARM®-based Systems <br>
:*Composed of Four Functions<br>
:**Two-pin UART<br>
:**Debug Communication Channel (DCC) Support<br>
:**Chip ID Registers<br>
:**ICE Access Prevention<br>
:*Two-pin UART<br>
:**Implemented Features are USART Compatible <br>
:**Independent Receiver and Transmitter with  a Common Programmable Baud Rate Generator<br>
:**Even, Odd, Mark or Space Parity Generation<br>
:**Parity, Framing and Overrun Error Detection<br>
:**Automatic Echo, Local Loopback and Remote Loopback Channel Modes<br>
:**Interrupt Generation<br>
:**Support for Two DMA Channels with Connection to Receiver and Transmitter<br>
:*Debug Communication Channel Support<br>
:**Offers Visibility of COMMRX and COMM TX Signals from the ARM Processor<br>
:**Interrupt Generation<br>
:*Chip ID Registers<br>
:**Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals<br>
:*ICE Access Prevention<br>
:**Enables Software to Prevent System Access Through the ARM Processor’s ICE<br>
:**Prevention is Made by Asserting the NTRST Line of the ARM Processor’s ICE<br>
=== UART === 
:*Two-pin UART<br>
:**Independent Receiver and Transmitter with  a Common Programmable Baud Rate Generator<br>
:**Even, Odd, Mark or Space Parity Generation<br>
:**Parity, Framing and Overrun Error Detection<br>
:**Automatic Echo, Local Loopback and Remote Loopback Channel Modes<br>
:**Interrupt Generation<br>
:**Support for Two DMA Channels with Connection to Receiver and Transmitter<br>
=== USART === 
:*Programmable Baud Rate Generator<br>
:*5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications<br>
:**1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode<br>
:**Parity Generation and Error Detection<br>
:**Framing Error Detection, Overrun Error Detection<br>
:**MSB- or LSB-first<br>
:**Optional Break Generation and Detection<br>
:**By 8 or by 16 Over-sampling Receiver Frequency<br>
:**Optional Hardware Handshaking RTS-CTS<br>
:**Receiver Time-out and Transmitter Timeguard<br>
:**Optional Multidrop Mode with Address Generation and Detection<br>
:*RS485 with Driver Control Signal<br>
:*ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards<br>
:**NACK Handling, Error Counter with Repetition and Iteration Limit<br>
:**IrDA Modulation and Demodulation<br>
:**Communication at up to 115.2 Kbps<br>
:*SPI Mode<br>
:**Master or Slave<br>
:**Serial Clock Programmable Phase and Polarity<br>
:**SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6<br>
:*Test Modes<br>
:**Remote Loopback, Local Loopback, Automatic Echo<br>
:*Supports Connection of:<br>
:**Two DMA Controller Channels (DMAC)<br>
:*Offers Buffer Transfer without Processor Intervention<br>
=== CAN === 
:*Fully Compliant with CAN 2.0 Part A and 2.0 Part B<br>
:*Bit Rates up to 1 Mbit/s<br>
:*8 Object Oriented Mailboxes  with the Following Properties:<br>
:**CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message<br>
:**Object Configurable in Receive (with Overwrite or Not) or Transmit Modes<br>
:**Independent 29-bit Identifier and Mask Defined for Each Mailbox<br>
:**32-bit Access to Data Registers for Each Mailbox Data Object<br>
:**Uses a 16-bit Timestamp on Receive and Transmit Messages<br>
:**Hardware Concatenation of ID Masked Bitfields To Speed Up Family ID Processing<br>
:*16-bit Internal Timer for Timestamping and Network Synchronization<br>
:*Programmable Reception Buffer Length up to 8 Mailbox Objects<br>
:*Priority Management between Transmission Mailboxes<br>
:*Autobaud and Listening Mode<br>
:*Low Power Mode and Programmable Wake-up on Bus Activity or by the Application<br>
:*Data, Remote, Error and Overload Frame Handling<br>
:*Write Protected Registers<br>
=== PWM === 
:*Channels<br>
:*Common Clock Generator Providing Thirteen Different Clocks <br>
:**A Modulo n Counter Providing Eleven Clocks<br>
:**Two Independent Linear Dividers Working on Modulo n Counter Outputs<br>
:*Independent Channels<br>
:**Independent 16-bit Counter for Each Channel<br>
:**Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or Non-Overlapping Time) for Each Channel<br>
:**Independent Enable Disable Command for Each Channel<br>
:**Independent Clock Selection for Each Channel<br>
:**Independent Period, Duty-Cycle and Dead-Time for Each Channel<br>
:**Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel<br>
:**Independent Programmable Selection of The Output Waveform Polarity for Each Channel<br>
:**Independent Programmable Center or Left Aligned Output Waveform for Each Channel<br>
:**Independent Output Override for Each Channel<br>
:**Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration <br>
:*2 2-bit Gray Up/Down Channels for Stepper Motor Control<br>
:*Synchronous Channel Mode<br>
:**Synchronous Channels Share the Same Counter <br>
:**Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods<br>
:*2 Independent Events Lines Intended to Synchronize ADC Conversions<br>
:**Programmable delay for Events Lines to delay ADC measurements<br>
:*8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines<br>
:*1 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs<br>
:**4 User Driven through PIO inputs<br>
:**PMC Driven when Crystal Oscillator Clock Fails<br>
:**ADC Controller Driven through Configurable Comparison Function<br>
:*Write Protected Registers<br>
=== ADC === 
:*12-bit Resolution <br>
:*1 MHz Conversion Rate<br>
:*Wide Range Power Supply Operation<br>
:*Selectable Single Ended or Differential Input Voltage<br>
:*Programmable Gain For Maximum Full Scale Input Range 0 - VDD<br>
:*Resistive 4-wire and 5-wire Touchscreen Controller<br>
:**Position and Pressure Measurement for 4-wire screens<br>
:**Position Measurement for 5-wire screens<br>
:**Average of up to 8 measures for noise filtering<br>
:*Programmable Pen Detection sensitivity<br>
:*Integrated Multiplexer Offering Up to 12 Independent Analog Inputs<br>
:*Individual Enable and Disable of Each Channel<br>
:*Hardware or Software Trigger<br>
:**External Trigger Pin<br>
:**Timer Counter Outputs (Corresponding TIOA Trigger)<br>
:**Internal Trigger Counter<br>
:**Trigger on Pen Contact Detection<br>
:**PWM Event Line<br>
:*Drive of PWM Fault Input<br>
:*DMA Support<br>
:*Possibility of ADC Timings Configuration<br>
:*Two Sleep Modes and Conversion Sequencer<br>
:**Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels<br>
:**Possibility of Customized Channel Sequence<br>
:*Standby Mode for Fast Wakeup Time Response<br>
:**Power Down Capability<br>
:*Automatic Window Comparison of Converted Values<br>
:**Write Protect Registers<br>