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| − | === 接口说明 ===
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| − | '''CCM(Clock Control Module):'''<br>
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| − | These modules are responsible for clock.<br>
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| − | '''ECSPI(Enhanced Configurable SPI):'''<br>
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| − | Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s. It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. <br>
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| − | '''ENET(Ethernet Controller):'''<br>
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| − | The Ethernet Media Access Controller (MAC) is designed to support 10/100 Mbit/s Et hernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The module has dedicated hardware to support the IEEE 1588 standard.<br>
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| − | '''FLEXCAN(Flexible Controller Area Network):'''<br>
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| − | The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the Electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. <br>
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| − | '''GPIO(General Purpose I/O Modules):'''<br>
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| − | Used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O.<br>
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| − | '''LCDIF(LCD interface):'''<br>
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| − | The LCDIF is a general purpose display controller used to drive a wide range of display devices varying in size and capability. The LCDIF is designed to support dumb (synchronous 24-bit Parallel RGB interface) and smart (asynchronous parallel MPU interface) LCD devices.<br>
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| − | '''PWM(Pulse Width Modulation):'''<br>
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| − | The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can al so generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound.<br>
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| − | '''SJC(System JTAG Controller):'''<br>
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| − | The SJC provides JTAG interface, which complies with JTAG TAP standards, to internal logic. The i.MX 6UltraLite processors use JTAG port for production, testing, and system debugging. In addition, the SJC provides BSR (Boundary Scan Register) standard support, which complies with IEEE1149.1 and IEEE1149.6 standards. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities.<br>
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| − | '''UART(UART Interface):'''<br>
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| − | Each of the UART modules support the following serial data transmit/receive protocols and configurations: <br>
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| − | • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none)<br>
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| − | • Programmable baud rates up to 5 Mbps.<br>
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| − | • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud<br>
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| − | '''uSDHC(Ultra Secured Digital Host Controller):''' <br>
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| − | i.MX 6UltraLite specif ic SoC characteristics:<br>
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| − | All four MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. They are:<br>
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| − | • Fully compliant with MMC command/response sets and Physical Layer as defined in the Multimedia Card System Specification, v4.5/4.2/4.3/4.4/4.41/ including high-capacity (size > 2 GB) cards HC MMC. <br>
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| − | • Fully compliant with SD command/response sets and Physical Layer as defined in the SD Memory Card Specifications, v3.0 including high-capacity SDXC cards up to 2 TB.<br>
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| − | • Fully compliant with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v3.0<br>
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| − | Two ports support:<br>
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| − | • 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max)<br>
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| − | • 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max)<br>
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| − | • 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode (200 MB/s max)<br>
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| − | '''USB(Universal Serial Bus 2.0):'''<br>
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| − | USBO2 (USB OTG1 and USB OTG2) contains:<br>
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| − | • Two high-speed OTG 2.0 modules with integrated HS USB PHYs<br>
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| − | • Support eight Transmit (TX) and eight Receive (Rx) endpoints, including endpoint 0<br>
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| − | '''WDOG(Watch Dog):'''<br>
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| − | The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line.<br>
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| | == '''管脚定义''' == | | == '''管脚定义''' == |
