MYZR-RK3399-MB314 硬件介绍

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接口功能


电源接口

MYZR-RK3399_CB314 模块电源接口定义如下表所示:

管脚号 管脚定义 I/O属性 功能描述
P1 ~ P9 VCC_SYS PI 模块工作电源输入,5V/3A
P10 VCC_RTC PI RTC 实时时钟电源输入,3.3V供电
S10~S12 VCC3V3_SYS PO 3.3V输出,峰值可达2A
S13~S15 VCC_1V8 PO 1.8V输出,峰值可达 1A
S16、S17 VCCA3V0_CODEC0 PO 3.0V输出,峰值可达 300mA
S18、S19 VCCA1V8_CODEC0 PO 1.8V输出,峰值可达 300mA
S20 VCC1V8_DVP PO 1.8V输出,峰值可达 150mA
P11、P23、P31、P42、P58、P74、P81、P89、P100、P109、P119、P133、P140、P147、P154~P156、

S1~S9、S21、S22、S26、S47、S50、S53、S56、S59、S62、S65、S76、S79、S82、S85、S88、S91、

S94、S97、S100、S103、S106、S108、S110、S112、S115、S118、S121、S124、S127、S130、S133、

S136、S137、S140、S143、S146、S149、S152、S155、S158

GND -

MYZR-RK3399_CB314 模块使用 VCC_SYS 供电,为保证模块能正常运行,供电电源电压不低于4.6V,不超过 5.5V,供电电流不低于 3A。建议在模块供电端口加一个大于 470uF 的电容。


多媒体接口

EDP接口

MYZR-RK3399_CB314 模块eDP接口定义如下表所示:

模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
S144 EDP_TX3P D30 EDP_TX3P O eDP data lane3 positive output
S145 EDP_TX3N D31 EDP_TX3N O eDP data lane3 negative output
S147 EDP_TX2P C30 EDP_TX2P O eDP data lane2 positive output
S148 EDP_TX2N C31 EDP_TX2N O eDP data lane2 negative output
S150 EDP_TX1P B30 EDP_TX1P O eDP data lane1 positive output
S151 EDP_TX1N A30 EDP_TX1N O eDP data lane1 negative output
S153 EDP_TX0P B29 EDP_TX0P O eDP data lane0 positive output
S154 EDP_TX0N A29 EDP_TX0N O eDP data lane0 negative output
S156 EDA_AUXP B28 EDPAUXP I/O eDP CH-AUX positive differential output
S157 EDA_AUXN A28 EDPAUXN I/O eDP CH-AUX negative differential output

eDP 走线请注意:

  • eDP 信号的参考时钟建在数据中,在接收端还原出时钟信号,所以四组数据差分线对组间不做等长,只需做组内等长处理;
  • 为抑制电磁辐射,eDP信号建议PCB内层走线,并保证走线参考面是一个连续完整的参考面,不被分割,否则会造成差分线阻抗的不连续性并引入外部噪声对的影响。如在PCB表层走线,请注意用地线做包地处理;差分对之间不需要伴随地走线;

eDP走线要求如表:

参数 要求
Trace Impedance 100Ω ±10% differential
Max intra-pair skew < 4 ps
Max trace length on carrier board < 6 inch
Minimum pair to pair spacing > 3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
AC coupling capacitors 100nF ±20%, discrete 0201 package preferable
The minimum spacing between EDP and other Signals At least 3 times the width of EDP trace.
Maximum allowed via 4

HDMI接口

MYZR-RK3399_CB314 模块HDMI接口定义如下表所示:

模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
S48 I2C3_SDA_3V3 AG6 GPIO4_C0/I2C3_SDA/UART2B_RX_u IO I2C data line for HDMI
S49 I2C3_SCL_3V3 AL2 GPIO4_C1/I2C3_SCL/UART2B_TX_u IO I2C clock line for HDMI
S66 HDMI_CEC AD7 GPIO4_C7/HDMI_CECINOUT/EDP_HOTPLUG_u IO HDMI CEC signal
S67 HDMI_TXCP AK16 HDMI_TXCP O HDMI positive TMDS differential line driver clock output
S68 HDMI_TXCN AL16 HDMI_TXCN O HDMI negative TMDS differential line driver clock output
S69 HDMI_TX0P AK17 HDMI_TX0P O HDMI positive TMDS differential line0 driver data output
S70 HDMI_TX0N AL17 HDMI_TX0N O HDMI negative TMDS differential line0 driver data output
S71 HDMI_TX1P AK18 HDMI_TX1P O HDMI positive TMDS differential line1 driver data output
S72 HDMI_TX1N AL18 HDMI_TX1N O HDMI negative TMDS differential line1 driver data output
S73 HDMI_TX2P AK19 HDMI_TX2P O HDMI positive TMDS differential line2 driver data output
S74 HDMI_TX2N AL19 HDMI_TX2N O HDMI negative TMDS differential line2 driver data output
S75 PORT_HPD AE15 HDMI_HPD IO HDMI hot plug detect signal

HDMI走线请注意:

  • HDMI TX信号的参考时钟为HDMI TXC,所以包括时钟在内的四组差分对都需要做等长处理;
  • HDMI信号需要保证走线参考面是一个连续完整的参考面,不被分割, 否则会造成差分线阻抗的不连续性并引入外部噪声对的影响。在PCB表层走线请注意用地线做整组包地处理; 差分对之间不需要伴随地走线;
  • HDMI信号可以直接顺序扇出到HDMI连接座,走线中应该尽可能的减少换层过孔,过孔会造成线路阻抗的不连续;如果因为模具结构无法避免换层,建议将换层的阻抗变化控制在10%以内,并在每对换层的差分对旁边就近安排一个GND过孔用于信号回流路径的换层;
  • ESD器件靠近HDMI连接座放置;
  • 使用带屏蔽层的HDMI线缆,能有效改善EMI问题;

HDMI走线要求如表:

参数 要求
Trace Impedance 100Ω ±10%
Max intra-pair skew < 4ps
Max trace length skew between clock and data pairs < 80ps
Max trace length on carrier board < 9.8 inchs
Minimum pair to pair spacing > 3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible
The minimum spacing between HDMI and other Signals At least 3 times the width of HDMI trace
Maximum allowed via 4

MIPI接口

MYZR-RK3399_CB314 模块MIPI接口定义如下表所示:

  • MIPI DSI接口定义
模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
S51 MIPI_TX0_D3N AH9 MIPI_TX0_D3N IO MIPI DSI negative differential data line3 transceiver output
S52 MIPI_TX0_D3P AG9 MIPI_TX0_D3P IO MIPI DSI positive differential data line3 transceiver output
S54 MIPI_TX0_D2N AH11 MIPI_TX0_D2N IO MIPI DSI negative differential data line2 transceiver output
S55 MIPI_TX0_D2P AG11 MIPI_TX0_D2P IO MIPI DSI positive differential data line2 transceiver output
S57 MIPI_TX0_CLKN AH12 MIPI_TX0_CLKN IO MIPI DSI negative differential clock line transceiver output
S58 MIPI_TX0_CLKP AG12 MIPI_TX0_CLKP IO MIPI DSI positive differential clock line transceiver output
S60 MIPI_TX0_D1N AH14 MIPI_TX0_D1N IO MIPI DSI negative differential data line1 transceiver output
S61 MIPI_TX0_D1P AG14 MIPI_TX0_D1P IO MIPI DSI positive differential data line1 transceiver output
S63 MIPI_TX0_D0N AH15 MIPI_TX0_D0N IO MIPI DSI negative differential data line0 transceiver output
S64 MIPI_TX0_D0P AG15 MIPI_TX0_D0P IO MIPI DSI positive differential data line0 transceiver output
  • MIPI CSI/DSI接口定义
模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
S77 MIPI_TX1/RX1_D1N AL7 MIPI_TX1/RX1_D1N IO MIPI CSI/DSI negative differential data line1 transceiver output
S78 MIPI_TX1/RX1_D1P AK7 MIPI_TX1/RX1_D1P IO MIPI CSI/DSI positive differential data line1 transceiver output
S80 MIPI_TX1/RX1_D0N AL6 MIPI_TX1/RX1_D0N IO MIPI CSI/DSI negative differential data line0 transceiver output
S81 MIPI_TX1/RX1_D0P AK6 MIPI_TX1/RX1_D0P IO MIPI CSI/DSI positive differential data line0 transceiver output
S83 MIPI_TX1/RX1_D2N AL9 MIPI_TX1/RX1_D2N IO MIPI CSI/DSI negative differential data line2 transceiver output
S84 MIPI_TX1/RX1_D2P AK9 MIPI_TX1/RX1_D2P IO MIPI CSI/DSI positive differential data line2 transceiver output
S86 MIPI_TX1/RX1_CLKP AK8 MIPI_TX1/RX1_CLKP IO MIPI CSI/DSI negative differential clock line transceiver output
S87 MIPI_TX1/RX1_CLKN AL8 MIPI_TX1/RX1_CLKN IO MIPI CSI/DSI positive differential clock line transceiver output
S89 MIPI_TX1/RX1_D3P AK10 MIPI_TX1/RX1_D3P IO MIPI CSI/DSI negative differential data line3 transceiver output
S90 MIPI_TX1/RX1_D3N AL10 MIPI_TX1/RX1_D3N IO MIPI CSI/DSI positive differential data line3 transceiver output
  • MIPI CSI接口定义
模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
S92 MIPI_RX0_D0P AK15 MIPI_RX0_D0P IO MIPI CSI positive differential data line0 transceiver output
S93 MIPI_RX0_D0N AL15 MIPI_RX0_D0N IO MIPI CSI negative differential data line0 transceiver output
S95 MIPI_RX0_D1P AK14 MIPI_RX0_D1P IO MIPI CSI positive differential data line1 transceiver output
S96 MIPI_RX0_D1N AL14 MIPI_RX0_D1N IO MIPI CSI negative differential data line1 transceiver output
S98 MIPI_RX0_CLKP AK13 MIPI_RX0_CLKP IO MIPI DSI positive differential clock line transceiver output
S99 MIPI_RX0_CLKN AL13 MIPI_RX0_CLKN IO MIPI DSI negative differential clock line transceiver output
S101 MIPI_RX0_D2P AK12 MIPI_RX0_D2P IO MIPI CSI positive differential data line2 transceiver output
S102 MIPI_RX0_D2N AL12 MIPI_RX0_D2N IO MIPI CSI negative differential data line2 transceiver output
S104 MIPI_RX0_D3P AK11 MIPI_RX0_D3P IO MIPI CSI positive differential data line3 transceiver output
S105 MIPI_RX0_D3N AL11 MIPI_RX0_D3N IO MIPI CSI negative differential data line3 transceiver output

MIPI DSI:

  • 单MIPI工作模式下,必须使用MIPI_DSI0,即MIPI_TX0这组; MIPI-DSI1不能被单独使用;
  • 双MIPI工作模式下,MIPI_TX0和MIPI_TX1/RX1通道可以根据布局以及走线需要,整组调换使用;

MIPI CSI:

  • RK3399有两组MIPI-CSI输入,均内置ISP处理器,在双MIPI输入的时候可以同时使用。

MIPI 走线请注意:

  • 为抑制电磁辐射, MIPI信号建议PCB内层走线,并保证走线参考面是一个连续完整的参考面,不被分割, 否则会造成差分线阻抗的不连续性并引入外部噪声对的影响。如在PCB表层走线,请注意用地线做包地处理; 差分对之间不需要伴随地走线;
  • MIPI信号在设置走线的延时时,请尽量靠近RK3399端;

MIPI 走线要求如表:

参数 要求
Trace Impedance 100Ω ±10% differential
Max intra-pair skew < 4ps
Max trace length skew between clock and data pairs < 7ps
Max trace length < 7.2inch
Maximum allowed via Minimize the number of via in each lane
Minimum pair to pair spacing > 3 times the width of the trace.Try to increase Spacing between pairs whenever it is possible.
The minimum spacing between Mipi and other Signals At least 3 times the width of Mipi trace.

CIF接口

MYZR-RK3399_CB314 模块CIF接口定义如下表所示:

模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
P120 CIF_D4 H29 GPIO2_A4/VOP_D4/CIF_D4_d I Camera interface input pixel data4
P121 CIF_D6 H27 GPIO2_A6/VOP_D6/CIF_D6_d I Camera interface input pixel data6
P122 CIF_CLKO H31 GPIO2_B3/SPI2_CLK/VOP_DEN/CIF_CLKOUTA_u O Camera interface output work clock
P123 CIF_D1 H25 GPIO2_A1/VOP_D1/CIF_D1/I2C2_SCL_u I Camera interface input pixel data1
P124 CIF_D0 G31 GPIO2_A0/VOP_D0/CIF_D0/I2C2_SDA_u I Camera interface input pixel data0
P125 CIF_D7 G30 GPIO2_A7/VOP_D7/CIF_D7/I2C7_SDA_u I Camera interface input pixel data7
P126 DVP_PDN0_H F31 GPIO2_B4/SPI2_CSn0_u IO
P127 CIF_VSYNC H28 GPIO2_B0/VOP_CLK/CIF_VSYNC/I2C7_SCL_u I Camera interface vertical sync signal
P128 CIF_D2 H30 GPIO2_A2/VOP_D2/CIF_D2_d I Camera interface input pixel data2
P129 CIF_CLKI H24 GPIO2_B2/SPI2_TXD/CIF_CLKIN/I2C6_SCL_u I Camera interface input pixel clock
P130 CIF_HREF F30 GPIO2_B1/SPI2_RXD/CIF_HREF/I2C6_SDA_u I Camera interface horizontial sync signal
P131 CIF_D3 F28 GPIO2_A3/VOP_D3/CIF_D3_d I Camera interface input pixel data3
P132 CIF_D5 F29 GPIO2_A5/VOP_D5/CIF_D5_d I Camera interface input pixel data5

I2S/PCM接口

MYZR-RK3399_CB314 模块I2S/PCM接口定义如下表所示:

  • I2S/PCM接口定义
模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
P12 I2S_CLK AC7 GPIO4_A0/I2S_CLK_d IO I2S/PCM clock source, shared by I2S0 and I2S1
  • I2S0/PCM0接口定义
模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
P13 I2S0_SDI1 AE5 GPIO3_D4/I2S0_SDI1SDO3_d IO I2S/PCM serial data input[1] or output [3]
P14 I2S0_SCLK AG3 GPIO3_D0/I2S0_SCLK_d IO I2S/PCM serial clock
P15 I2S0_LRCK_RX AF4 GPIO3_D1/I2S0_LRCK_RX_d IO I2S/PCM left & right channel signal for receiving serial data,synchronous left & right channel

in I2S mode and the beginning of a group of left & right channels in PCM mode

P16 I2S0_LRCK_TX AJ2 GPIO3_D2/I2S0_LRCK_TX_d IO I2S/PCM left & right channel signal for transmitting serial data, synchronous left & right channel

in I2S mode and the beginning of a group of left & right channels in PCM mode

P17 I2S0_SDI0 Y7 GPIO3_D3/I2S0_SDI0_d IO I2S/PCM serial data input[0]
P18 I2S0_SDO2 AA6 GPIO3_D5/I2S0_SDI2SDO2_d IO I2S/PCM serial data input [2] or output [2]
P19 I2S0_SDO1 AH2 GPIO3_D6/I2S0_SDI3SDO1_d IO I2S/PCM serial data input [3] or output [1]
P20 I2S0_SDO0 AH1 GPIO3_D7/I2S0_SDO0_d IO I2S/PCM serial data output [0]
  • I2S1/PCM1接口定义
模块管脚号 模块管脚定义 CPU 管脚号 CPU 管脚定义 I/O属性 功能描述
P24 I2S1_SCLK_BT_PCM AF3 GPIO4_A3/I2S1_SCLK_d IO I2S/PCM serial clock
P25 I2S1_LRCK_RX_BT_PCM AA7 GPIO4_A4/I2S1_LRCK_RX_d IO I2S/PCM left & right channel signal for receiving serial data,synchronous left & right channel

in I2S mode and the beginning of a group of left & right channels in PCM mode

P26 I2S1_LRCK_TX_BT_PCM AJ1 GPIO4_A5/I2S1_LRCK_TX_d IO I2S/PCM left & right channel signal for transmitting serial data, synchronous left & right channel

in I2S mode and the beginning of a group of left & right channels in PCM mode

P27 I2S1_SDI0_BT_PCM AD6 GPIO4_A6/I2S1_SDI0_d IO I2S/PCM serial data input [0]
P28 I2S1_SDO0_BT_PCM AC6 GPIO4_A7/I2S1_SDO0_d IO I2S/PCM serial data output [0]

I2S/PCM走线请注意:

  • I2S/PCM在PCB布线上相邻的参考层要保持完整(相邻层要保持是同一个平面), 避免一些电源等其他信号的干扰, 且与同一层的其他的线有GND隔离